DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 340
DF2372VFQ34V
Manufacturer Part Number
DF2372VFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 340 of 1208
- Download datasheet (8Mb)
Section 6 Bus Controller (BSC)
6.11.3
Figure 6.84 shows the timing for transition to the bus released state.
Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Rev.7.00 Mar. 18, 2009 page 272 of 1136
REJ09B0109-0700
Address bus
HWR, LWR
Data bus
BREQO
BREQ
BACK
RD
AS
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
φ
Transition Timing
At least one state from sampling of BREQ signal.
bus release while BREQOE bit is set to 1, BREQO signal goes low.
External space
access cycle
T
Figure 6.84 Bus Released State Transition Timing
1
[1]
T
2
[2]
[3]
[4]
[5]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
[6]
[7]
[8]
CPU
cycle
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