DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 487
DF2372VFQ34V
Manufacturer Part Number
DF2372VFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 487 of 1208
- Download datasheet (8Mb)
Section 8 EXDMA Controller (EXDMAC)
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the
block transfer was not carried out normally.
When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.
Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby
mode and by a reset. DMA transfer is not guaranteed in these cases.
8.4.13
Relationship between EXDMAC and Other Bus Masters
The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external
bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never
occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or
external bus release state may be inserted after the write cycle. As the internal bus masters are of
lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.
The EXDMAC releases the bus in the following cases:
1. When DMA transfer is performed in cycle steal mode
2. When switching to a different channel
3. When transfer ends in burst transfer mode
4. When transfer of one block ends in block transfer mode
5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1
(however, the bus is not released between read and write cycles)
Rev.7.00 Mar. 18, 2009 page 419 of 1136
REJ09B0109-0700
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