R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1150
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 25 Flash Memory
Memory MAT switching is enabled by setting FMATS. However note that access to a memory
MAT is not allowed until memory MAT switching is completed. During memory MAT switching,
the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt
vector is read is undetermined. Perform memory MAT switching in accordance with the
description in section 25.11, Switching between User MAT and User Boot MAT.
Except for memory MAT switching, the erasing procedure is the same as that in user program
mode.
The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT,
and external space) is shown in section 25.8.5, On-Chip Program and Storable Area for Program
Data.
25.8.5
In the descriptions in this manual, the on-chip programs and program data storage areas are
assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory
which is not to be programmed or erased as long as the following conditions are satisfied.
1. The on-chip program is downloaded to and executed in the on-chip RAM specified by
2. Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack
3. Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip
4. In an operating mode in which the external address space is not accessible, such as single-chip
5. The flash memory is not accessible during programming/erasure. Programming/erasure is
6. After programming/erasure starts, access to the flash memory should be inhibited until FKEY
Rev. 1.00 Jan. 29, 2010 Page 1118 of 1380
REJ09B0596-0100
FTDAR. Therefore, this on-chip RAM area is not available for use.
area.
RAM because it will require switching of the memory MATs.
mode, the required procedure programs, NMI handling vector table, and NMI handling routine
should be transferred to the on-chip RAM before programming/erasure starts (download result
is determined).
executed by the program downloaded to the on-chip RAM. Therefore, the procedure program
that initiates operation, the NMI handling vector table, and the NMI handling routine should be
stored in the on-chip RAM other than the flash memory.
is cleared. The reset input state (period of RES = 0) must be set to at least 100 μs when the
operating mode is changed and the reset start executed on completion of programming/erasure.
Transitions to the reset state are inhibited during programming/erasure. When the reset signal
is input, a reset input state (period of RES = 0) of at least 100 μs is needed before the reset
signal is released.
On-Chip Program and Storable Area for Program Data
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