R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1160
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 25 Flash Memory
Figure 25.20 shows an example of overlaying flash memory block area EB0.
The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in
RAMER from among the eight blocks, EB0 to EB7, of the user MAT.
To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in
RAMER to 1 and bits RAM2 to RAM0 to B'000.
For programming/erasing the user MAT, the procedure programs including a download program
of the on-chip program must be executed. At this time, the download area should be specified so
that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area
in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the
tuned data must be saved in an unused area beforehand.
Rev. 1.00 Jan. 29, 2010 Page 1128 of 1380
REJ09B0596-0100
Figure 25.20 Address Map of Overlaid RAM Area (H8SX/1668)
H'0FFFFF
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
Flash memory
EB8 to EB23
user MAT
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
This area can be accessed via
both the on-chip RAM and flash
memory area.
On-chip RAM
H'FF6000
H'FFA000
H'FFAFFF
H'FFBFFF
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