R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1294

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 29 List of Registers
Rev. 1.00 Jan. 29, 2010 Page 1262 of 1380
REJ09B0596-0100
Register Name
Timer status register_0
Timer counter_0
Timer general register A_0
Timer general register B_0
Timer general register C_0
Timer general register D_0
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Timer control register_3
Timer mode register_3
Timer I/O control register H_3
Timer I/O control register L_3
Timer interrupt enable register_3
Timer status register_3
Timer counter_3
Timer general register A_3
Timer general register B_3
Abbreviation
TSR_0
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TCNT_1
TGRA_1
TGRB_1
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TCNT_2
TGRA_2
TGRB_2
TCR_3
TMDR_3
TIORH_3
TIORL_3
TIER_3
TSR_3
TCNT_3
TGRA_3
TGRB_3
Number
of Bits
8
16
16
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
8
16
16
16
Address
H'FFFC5
H'FFFC6
H'FFFC8
H'FFFCA
H'FFFCC
H'FFFCE
H'FFFD0
H'FFFD1
H'FFFD2
H'FFFD4
H'FFFD5
H'FFFD6
H'FFFD8
H'FFFDA
H'FFFE0
H'FFFE1
H'FFFE2
H'FFFE4
H'FFFE5
H'FFFE6
H'FFFE8
H'FFFEA
H'FFFF0
H'FFFF1
H'FFFF2
H'FFFF3
H'FFFF4
H'FFFF5
H'FFFF6
H'FFFF8
H'FFFFA
Module
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
Data
Width
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ