R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 14

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.7
9.8
9.9
9.10
Rev. 1.00 Jan. 29, 2010 Page xiv of xxxii
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
9.6.7
Byte Control SRAM Interface .......................................................................................... 247
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
9.7.8
Burst ROM Interface ........................................................................................................ 255
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
Address/Data Multiplexed I/O Interface........................................................................... 260
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
9.9.10
DRAM Interface ............................................................................................................... 270
9.10.1
9.10.2
9.10.3
9.10.4
9.10.5
I/O Pins Used for Basic Bus Interface .............................................................. 234
Basic Timing..................................................................................................... 235
Wait Control ..................................................................................................... 241
Read Strobe (RD) Timing................................................................................. 243
Extension of Chip Select (CS) Assertion Period............................................... 244
DACK and EDACK Signal Output Timing...................................................... 246
Byte Control SRAM Space Setting................................................................... 247
Data Bus ........................................................................................................... 247
I/O Pins Used for Byte Control SRAM Interface ............................................. 248
Basic Timing..................................................................................................... 249
Wait Control ..................................................................................................... 251
Read Strobe (RD) ............................................................................................. 253
Extension of Chip Select (CS) Assertion Period............................................... 253
DACK and EDACK Signal Output Timing...................................................... 253
Burst ROM Space Setting................................................................................. 255
Data Bus ........................................................................................................... 255
I/O Pins Used for Burst ROM Interface............................................................ 256
Basic Timing..................................................................................................... 257
Wait Control ..................................................................................................... 259
Read Strobe (RD) Timing................................................................................. 259
Extension of Chip Select (CS) Assertion Period............................................... 259
Address/Data Multiplexed I/O Space Setting ................................................... 260
Address/Data Multiplex.................................................................................... 260
Data Bus ........................................................................................................... 260
I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 261
Basic Timing..................................................................................................... 262
Address Cycle Control...................................................................................... 264
Wait Control ..................................................................................................... 265
Read Strobe (RD) Timing................................................................................. 265
Extension of Chip Select (CS) Assertion Period............................................... 267
DACK and EDACK Signal Output Timing...................................................... 269
Setting DRAM Space........................................................................................ 270
Address Multiplexing ....................................................................................... 270
Data Bus ........................................................................................................... 271
I/O Pins Used for DRAM Interface .................................................................. 271
Basic Timing..................................................................................................... 272