R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1405

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Numerics
0 output/1 output..................................... 711
0-output/1-output .................................... 711
16-bit access space.................................. 232
16-bit counter mode................................ 802
16-bit timer pulse unit (TPU) ................. 667
32K timer (TM32K) ............................... 811
8-bit access space.................................... 231
8-bit timers (TMR) ................................. 777
A
A/D conversion accuracy...................... 1050
Absolute accuracy................................. 1050
Acknowledge ........................................ 1010
Address error .......................................... 112
Address map ............................................. 83
Address mode ......................................... 520
Address modes................................ 392, 471
Address/data multiplexed
I/O interface.................................... 224, 260
All-module-clock-stop mode ...... 1194, 1220
Area 0 ..................................................... 226
Area 1 ..................................................... 227
Area 2 ..................................................... 227
Area 3 ..................................................... 228
Area 4 ..................................................... 228
Area 5 ..................................................... 229
Area 6 ..................................................... 229
Area 7 ..................................................... 230
Area division........................................... 219
Asynchronous mode ............................... 875
AT-cut parallel-resonance type............. 1185
Available output signal and settings
in each port ............................................. 641
Average transfer rate generator............... 834
Index
B
Bφ clock output control......................... 1243
Basic bus interface .......................... 223, 234
Big endian ............................................... 222
Bit rate..................................................... 861
Bit synchronous circuit ......................... 1024
Block structure ...................................... 1070
Block transfer mode ................ 398, 476, 570
Boot mode................................... 1067, 1096
Boundary scan commands .................... 1167
Buffer operation ...................................... 716
Bulk-in transfer ....................................... 979
Bulk-out transfer ..................................... 978
Burst access mode................................... 404
Burst mode.............................................. 481
Burst ROM interface....................... 223, 255
Bus access modes.................................... 403
Bus arbitration......................................... 357
Bus configuration.................................... 210
Bus controller (BSC)............................... 173
Bus cycle division ................................... 564
Bus mode ................................................ 480
Bus release .............................................. 350
Bus width ................................................ 222
Bus-released state...................................... 72
Byte control SRAM interface ......... 223, 247
C
Cascaded connection............................... 802
Cascaded operation ................................. 720
Chain transfer.......................................... 571
Chip select signals................................... 220
Clock pulse generator ........................... 1179
Clock synchronization cycle (Tsy).......... 212
Clocked synchronous mode .................... 892
Cluster transfer dual address mode ......... 520
Rev. 1.00 Jan. 29, 2010 Page 1373 of 1380
REJ09B0596-0100