R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 224
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 9 Bus Controller (BSC)
9.2.8
BCR2 is used for bus arbitration control of the CPU, DMAC, EXDMAC, and DTC, and
enabling/disabling of the write data buffer function to the peripheral modules.
Rev. 1.00 Jan. 29, 2010 Page 192 of 1380
REJ09B0596-0100
Bit
7, 6
5
4
3, 2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
⎯
EBCCS
IBCCS
⎯
⎯
PWDBE
Bus Control Register 2 (BCR2)
⎯
R
7
0
Initial
Value
All 0
0
0
All 0
1
0
⎯
R
6
0
R/W
R
R/W
R/W
R
R/W
R/W
EBCCS
R/W
5
0
Description
Reserved
These are read-only bits and cannot be modified.
External Bus Cycle Control Select
Selects the method for external bus arbitration.
0: Releases the bus depending on the priority
1: Executes the bus cycle alternatively when a conflict
Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 1. The write value should
always be 1.
Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
bus mastership request conflicts with a DMAC or
DTC bus mastership request
IBCCS
occurs between a bus request by the EXDMAC,
external bus master or refresh bus and a request for
an external space access by the CPU, DMAC, or
DTC.
R/W
4
0
⎯
R
3
0
⎯
R
2
0
R/W
⎯
1
1
PWDBE
R/W
0
0
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