R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 292
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 9 Bus Controller (BSC)
9.9
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this
LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed
I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly
to this LSI.
9.9.1
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be
specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in
MPXCR.
9.9.2
In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 9.18
shows the relationship between the bus width and address output.
Table 9.18 Address/Data Multiplex
9.9.3
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.
For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,
D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is
accessed, the corresponding address will be output to the address bus.
For details on access size and data alignment, see section 9.5.6, Endian and Data Alignment.
Rev. 1.00 Jan. 29, 2010 Page 260 of 1380
REJ09B0596-0100
Bus Width
8 bits
16 bits
Address/Data Multiplexed I/O Interface
Address/Data Multiplexed I/O Space Setting
Address/Data Multiplex
Data Bus
Address
Data
Address
Data
Cycle
A15
D15
PI7
-
-
D14
A14
PI6
-
-
A13
D13
PI5
-
-
D12
A12
PI4
-
-
A11
D11
PI3
-
-
A10
D10
PI2
-
-
PI1
A9
D9
-
-
Data Pins
PI0
D8
A8
-
-
PH7
A7
D7
A7
D7
PH6
D6
D6
A6
A6
PH5
A5
D5
A5
D5
PH4
A4
D4
A4
D4
PH3
D3
D3
A3
A3
PH2
A2
D2
A2
D2
PH1
A1
D1
A1
D1
PH0
D0
D0
A0
A0
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