R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 328
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 9 Bus Controller (BSC)
9.11
In this LSI, area 2 in the external space can be used as the SDRAM interface space. Up to 8
Mbytes (64 Mbits) of DRAM is directly connected via the SDRAM interface. The CAS latency
with 2 to 4 is supported.
9.11.1
Area 2 can be specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR.
Table 9.24 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces.
In the SDRAM space, pins PB2, PB3, and PB4 are used as the RAS, CAS, and WE signals. The
PB1 pin is used as the CS2 signal by the PFCR setting, and the PB5 pin is used as the CKE signal
by setting the OEE bit in DRAMCR to 1. The bus settings of the SDRAM space depend on area 2
settings. The pin wait and program wait for the SDRAM space are not available. For PFCR, see
section 13, I/O Ports.
An SDRAM command is designated by the combination of the RAS, CAS, and WE signals and
the precharge-sel command (Precharge-sel) output on the upper column address.
This LSI supports the following commands: the NOP, auto-refresh (REF), self-refresh (SELF), all-
bank-precharge (PALL), bank active (ACTV), read (READ), write (WRIT), and mode register
setting (MRS). Commands controlling a bank are not supported.
Table 9.24 Relationship among DRAME and DTYPE and Area 2 Interfaces
[Legend]
X: Don't care
Rev. 1.00 Jan. 29, 2010 Page 296 of 1380
REJ09B0596-0100
DRAME
0
1
1
Synchronous DRAM Interface
Setting SDRAM space
DTYPE
X
0
1
Area 2 Interface
Basic bus space (initial state)/byte-control SRAM space
DRAM space
SDRAM space
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