R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 371
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(1)
If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits
IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read
cycle (n = 0 to 7).
Figure 9.93 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data conflict is prevented.
Figure 9.93 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)
Bφ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Consecutive Reads in Different Areas
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS1 = 0)
T
2
T
3
Data hold
time is long.
Bus cycle B
T
1
Data conflict
T
2
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Rev. 1.00 Jan. 29, 2010 Page 339 of 1380
Bus cycle A
T
1
(b) Idle cycle inserted
T
2
Section 9 Bus Controller (BSC)
T
3
Bus cycle B
T
i
REJ09B0596-0100
T
1
T
2
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