R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 373
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(3)
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).
Figure 9.95 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM
device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
Read after Write
Figure 9.95 Example of Idle Cycle Operation (Read after Write)
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS2 = 0)
T
2
Output floating
time is long.
T
3
Bus cycle B
T
1
T
2
Data conflict
Rev. 1.00 Jan. 29, 2010 Page 341 of 1380
T
(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Bus cycle A
1
T
2
(b) Idle cycle inserted
Section 9 Bus Controller (BSC)
T
3
T
Bus cycle B
i
REJ09B0596-0100
T
1
T
2
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