R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 451
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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10.5.9
Figure 10.23 shows an examples of signal timing of a basic bus cycle. In figure 10.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
Bφ
Address bus
RD
LHWR
LLWR
DMA Basic Bus Cycle
High
CPU cycle
Figure 10.23 Example of Bus Timing of DMA Transfer
Source address
T
1
T
2
T
1
DMAC cycle (one word transfer)
T
2
Destination address
T
3
Rev. 1.00 Jan. 29, 2010 Page 419 of 1380
T
1
Section 10 DMA Controller (DMAC)
T
2
T
3
REJ09B0596-0100
CPU cycle
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