R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 462

MCU FLASH 1024K ROM 144-LQFP

R5F61668MZN50FPV

Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668MZN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668MZN50FPV
Manufacturer:
REA
Quantity:
5
Part Number:
R5F61668MZN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 DMA Controller (DMAC)
(2)
In single address mode, data of one byte, one word, or one longword is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 10.35, the TEND signal output is enabled and data is transferred in bytes from the
external 8-bit 2-state access space to the external device in single address mode (write).
Rev. 1.00 Jan. 29, 2010 Page 430 of 1380
REJ09B0596-0100
Single Address Mode (Write and Cycle Stealing)
Address bus
LLWR
DACK
TEND
Figure 10.35 Example of Transfer in Single Address Mode (Byte Write)
released
Bus
DMA write
cycle
released
Bus
DMA write
cycle
released
Bus
DMA write
cycle
released
Bus
DMA write
Last transfer
cycle
cycle
released
Bus

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