R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 487
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit
31
Bit Name
DTE
Initial
value
0
R/W
R/W
Description
Data Transfer Enable
Enables or disables data transfer on the corresponding
channel. When this bit is set to 1, this indicates that an
EXDMA operation is in progress.
When auto-request mode is specified, transfer
processing begins when this bit is set to 1. With
external requests, transfer processing begins when a
transfer request is issued after this bit has been set to
1. When this bit is cleared to 0 during an EXDMA
operation, transfer is halted.
If this bit is cleared to 0 during an EXDMA operation in
block transfer mode, this bit is cleared to 0 on
completion of the currently executing one-block
transfer. When this bit is cleared to 0 during an EXDMA
operation in cluster transfer mode, this bit is cleared to
0 on completion of the currently executing one-cluster
transfer.
If an external source that ends (aborts) transfer occurs,
this bit is automatically cleared to 0 and transfer is
terminated.
Do not change the operating mode, transfer method, or
other parameters while this bit is set to 1.
0: Data transfer disabled
1: Data transfer enabled (during an EXDMA operation)
[Clearing conditions]
•
•
•
•
•
•
•
ends
interrupt
area overflow interrupt
interrupt
In block transfer mode, the value written is effective
after one-block transfer ends.
In cluster transfer mode, the value written is
effective after one-cluster transfer ends.
When transfer of the total transfer size specified
When operation is halted by a repeat size end
When operation is halted by an extended repeat
When operation is halted by a transfer size error
When 0 is written to terminate transfer
When an address error or NMI interrupt occurs
Reset, hardware standby mode
Rev. 1.00 Jan. 29, 2010 Page 455 of 1380
Section 11 EXDMA Controller (EXDMAC)
REJ09B0596-0100
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