R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 53
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
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1.4.3
Table 1.5
Classification
Power supply
Clock
Operating mode
control
System control
On-chip
emulator
Pin Functions
Pin Functions
Pin Name
V
V
V
PLLV
PLLV
DrV
DrV
XTAL
EXTAL
OSC1
OSC2
Bφ
SDRAMφ
MD3 to MD0 Input
MD_CLK
RES
STBY
EMLE
TRST
TMS
TDI
TCK
TDO
CC
CL
SS
CC
SS
CC
SS
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Description
Power supply pins. Connect them to the system power supply.
Connect this pin to V
be placed close to the pin).
Ground pins. Connect them to the system power supply (0 V).
Power supply pin for the PLL circuit. Connect them to the system
power supply.
Ground pin for the PLL circuit.
Power supply pin for the on-chip USB transceiver. Connect this pin
to the system power supply.
Ground pin for the on-chip USB transceiver.
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin. For an example of this connection, see
section 27, Clock Pulse Generator.
The 32.768 KH crystal resonator is connected to this pin.
The 32.768 KH crystal resonator is connected to this pin.
Outputs the system clock for external devices.
When connecting the synchronous DRAM, connect it to the CLK pin
of synchronous DRAM. For details, see section 9, Bus Controller
(BSC).
Pins for setting the operating mode. The signal levels on these pins
must not be changed during operation.
This pin changes the multiplication ratio of the clock oscillator. Do
not change values on this pin during operation.
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
This LSI enters hardware standby mode when this signal goes low.
Input pin for the on-chip emulator enable signal. The signal level
should normally be fixed low.
On-chip emulator pins or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator. When
the EMLE pin is driven low and to mode 3, these pins are dedicated
for the boundary scan mode.
SS
via a 0.1-μF capacitor (The capacitor should
Rev. 1.00 Jan. 29, 2010 Page 21 of 1380
Section 1 Overview
REJ09B0596-0100
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