R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 583
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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12.2.2
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Bit Name
CHNE
CHNS
DISEL
DTS
DTC Mode Register B (MRB)
Undefined
CHNE
⎯
7
Initial
Value
Undefined ⎯
Undefined ⎯
Undefined ⎯
Undefined ⎯
Undefined
CHNS
⎯
6
Undefined
R/W
DISEL
⎯
5
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
12.5.7, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Undefined
DTS
⎯
4
Undefined
DM1
⎯
3
Section 12 Data Transfer Controller (DTC)
Rev. 1.00 Jan. 29, 2010 Page 551 of 1380
Undefined
DM0
⎯
2
Undefined
⎯
⎯
1
REJ09B0596-0100
Undefined
⎯
⎯
0
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