R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 587
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668MZN50FPV
Manufacturer:
REA
Quantity:
5
Company:
Part Number:
R5F61668MZN50FPV
Manufacturer:
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Quantity:
10 000
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12.2.8
DTCCR specifies transfer information read skip.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
7 to 5
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to clear the flag.
Bit Name
⎯
Bit Name
DTCE15
DTCE14
DTCE13
DTCE12
DTCE11
DTCE10
DTCE9
DTCE8
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
DTC Control Register (DTCCR)
R/W
⎯
7
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Initial
Value
All 0
R/W
⎯
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
5
0
Description
DTC Activation Enable 15 to 0
Setting this bit to 1 specifies a relevant interrupt source to
a DTC activation source.
[Clearing conditions]
•
•
•
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
When writing 0 to the bit to be cleared after reading 1
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have ended
RRS
R/W
4
0
RCHNE
R/W
3
0
Section 12 Data Transfer Controller (DTC)
Rev. 1.00 Jan. 29, 2010 Page 555 of 1380
⎯
R
2
0
⎯
R
1
0
REJ09B0596-0100
R/(W)*
ERR
0
0
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