R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 64
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
R5F61668MZN50FPV
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Section 2 CPU
• Exception Vector Table and Memory Indirect Branch Addresses
• Stack Structure
Rev. 1.00 Jan. 29, 2010 Page 32 of 1380
REJ09B0596-0100
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The structure of the exception vector table is shown in
figure 2.2.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP
Notes: 1.
(a) Subroutine Branch
2.
3.
Figure 2.2 Exception Vector Table (Normal Mode)
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored on return.
H'0000
H'0001
H'0002
H'0003
Figure 2.3 Stack Structure (Normal Mode)
(16 bits)
PC
Reset exception vector
Reset exception vector
(SP*
SP
2
)
(b) Exception Handling
Exception
vector table
Reserved*
(16 bits)
CCR*
EXR*
CCR
PC
1
3
1,
*
3
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