R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 707
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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14.3.1
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
CCLR2
R/W
7
0
Initial
Value
0
0
0
0
0
0
0
0
CCLR1
R/W
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CCLR0
R/W
5
0
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 14.3 and 14.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. For details, see
table 14.5. When the input clock is counted using both
edges, the input clock period is halved (e.g. Pφ/4 both
edges = Pφ/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4
or slower. This setting is ignored if the input clock is Pφ/1,
or when overflow/underflow of another channel is
selected.
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 14.6 to 14.11 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 13, I/O Ports.
CKEG1
R/W
4
0
CKEG0
R/W
3
0
Rev. 1.00 Jan. 29, 2010 Page 675 of 1380
Section 14 16-Bit Timer Pulse Unit (TPU)
TPSC2
R/W
2
0
TPSC1
R/W
1
0
REJ09B0596-0100
TPSC0
R/W
0
0
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