R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 733
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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14.3.5
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to bits 5 to 0, to clear flags.
Bit Name
TGIED
TGIEC
TGIEB
TGIEA
Timer Status Register (TSR)
TCFD
R
7
1
Initial
value
0
0
0
0
⎯
⎯
6
1
R/W
R/W
R/W
R/W
R/W
R/(W)*
Description
TGR Interrupt Enable D
Enables/disables interrupt requests (TGID) by the TGFD bit
when the TGFD bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
TGR Interrupt Enable C
Enables/disables interrupt requests (TGIC) by the TGFC bit
when the TGFC bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable B
Enables/disables interrupt requests (TGIB) by the TGFB bit
when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable A
Enables/disables interrupt requests (TGIA) by the TGFA bit
when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
TCFU
5
0
R/(W)*
TCFV
4
0
R/(W)*
TGFD
3
0
Rev. 1.00 Jan. 29, 2010 Page 701 of 1380
Section 14 16-Bit Timer Pulse Unit (TPU)
R/(W)*
TGFC
2
0
R/(W)*
TGFB
1
0
REJ09B0596-0100
R/(W)*
TGFA
0
0
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