R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 801
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15.4.4
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• At compare match A, the NDR bits are always transferred to PODR.
• At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are
Figure 15.6 illustrates the non-overlapping pulse output operation.
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlapping margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
not transferred if their value is 1.
Pulse
output
pin
Non-Overlapping Pulse Output
Figure 15.6 Non-Overlapping Pulse Output
Normal output/inverted output
Q
NDER
PODR
Q
C
D
Section 15 Programmable Pulse Generator (PPG)
Rev. 1.00 Jan. 29, 2010 Page 769 of 1380
Q
NDR
Compare match A
Compare match B
D
Internal data bus
REJ09B0596-0100
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