R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 826
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 16 8-Bit Timers (TMR)
Rev. 1.00 Jan. 29, 2010 Page 794 of 1380
REJ09B0596-0100
Bit
6
5
4
3
2
Bit Name
CMFA
OVF
ADTE
OS3
OS2
Initial
Value
0
0
0
0
0
R/W
R/(W)*
R/(W)*
R/W
R/W
R/W
1
1
Description
Compare Match Flag A
[Setting condition]
•
[Clearing conditions]
•
•
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
When writing 0 after reading OVF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
A/D Trigger Enable*
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match A are
1: A/D converter start requests by compare match A are
Output Select 3 and 2*
These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
disabled
enabled
When TCNT matches TCORA
When writing 0 after reading CMFA = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When the DTC is activated by a CMIA interrupt while
the DISEL bit in MRB in the DTC is 0*
(toggle output)
3
2
3
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