R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 912
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 19 Serial Communication Interface (SCI, CRC)
19.4.5
Figure 19.9 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark
Figure 19.10 shows a sample flowchart for transmission in asynchronous mode.
Rev. 1.00 Jan. 29, 2010 Page 880 of 1380
REJ09B0596-0100
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt processing routine writes the next transmit data to TDR before
transmission of the current transmit data has finished, continuous transmission can be enabled.
multiprocessor bit (may be omitted depending on the format), and stop bit.
sent, and then serial transmission of the next frame is started.
state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TXI interrupt
request generated
TDRE
TEND
Figure 19.9 Example of Operation for Transmission in Asynchronous Mode
Serial Data Transmission (Asynchronous Mode)
1
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt processing
routine
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
TEI interrupt
request generated
0/1
Stop
bit
1
Idle state
(mark state)
1
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