R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 944
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 19 Serial Communication Interface (SCI, CRC)
Data transmission/reception using the DTC or DMAC is also possible in smart card interface
mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are
simultaneously set to 1, thus generating a TXI interrupt. This activates the DTC or DMAC by a
TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of
DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0
at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-transmits the
same data. During re-transmission, the TEND flag remains as 0, thus not activating the DTC or
DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of
bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR,
which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by
previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at
error occurrence.
When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or
DMAC prior to making SCI settings. For DTC or DMAC settings, see section 12, Data Transfer
Controller (DTC) and section 10, DMA Controller (DMAC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI
request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is
automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the RDRF
flag is not set but the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI
interrupt request is issued to the CPU instead; the error flag must be cleared.
Rev. 1.00 Jan. 29, 2010 Page 912 of 1380
REJ09B0596-0100
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