MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 113

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.6 Configuration Control Register
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
CME — Clock Monitor Enable Bit
Bit 2 — Unimplemented
CR[1:0] — COP Timer Rate Select Bit
EE[3:0] — EEPROM Mapping Bits
NOSEC — Security Mode Disable Bit
Reset:
Read:
Write:
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled, and when it is set, the clock monitor circuit is
enabled. Reset clears the CME bit.
Always reads 0
The internal E clock is first divided by 2
watchdog system. These control bits determine a scaling factor for
the watchdog timer. See
EE[3:0] apply only to MC68HC811E2. Refer to
Modes and On-Chip
Refer to
0 = Clock monitor circuit disabled
1 = Slow or stopped clocks cause reset
Figure 5-3. Configuration Control Register (CONFIG)
$103F
Bit 7
EE3
0
Section 4. Operating Modes and On-Chip
Resets and Interrupts
EE2
6
0
Memory.
EE1
5
0
Table 5-1
EE0
4
0
for specific timeout settings.
NOSEC
15
3
1
before it enters the COP
NOCOP
Section 4. Operating
2
1
Resets and Interrupts
Memory.
ROMON
1
1
Technical Data
EEON
Resets
Bit 0
1
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