MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 116

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resets and Interrupts
5.4.4 Real-Time Interrupt (RTI)
5.4.5 Pulse Accumulator
5.4.6 Computer Operating Properly (COP)
5.4.7 Serial Communications Interface (SCI)
Technical Data
116
The real-time interrupt flag (RTIF) is cleared and automatic hardware
interrupts are masked. The rate control bits are cleared after reset and
can be initialized by software before the real-time interrupt (RTI) system
is used.
The pulse accumulator system is disabled at reset so that the pulse
accumulator input (PAI) pin defaults to being a general-purpose
input pin.
The COP watchdog system is enabled if the NOCOP control bit in the
CONFIG register is cleared and disabled if NOCOP is set. The COP rate
is set for the shortest duration timeout.
The reset condition of the SCI system is independent of the operating
mode. At reset, the SCI baud rate control register (BAUD) is initialized to
$04. All transmit and receive interrupts are masked and both the
transmitter and receiver are disabled so the port pins default to being
general-purpose I/O lines. The SCI frame format is initialized to an 8-bit
character size. The send break and receiver wakeup functions are
disabled. The TDRE and TC status bits in the SCI status register (SCSR)
are both 1s, indicating that there is no transmit data in either the transmit
data register or the transmit serial shift register. The RDRF, IDLE, OR,
NF, FE, PF, and RAF receive-related status bits in the SCI control
register 2 (SCCR2) are cleared.
Resets and Interrupts
M68HC11E Family — Rev. 3.2
MOTOROLA