MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 117

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5.4.8 Serial Peripheral Interface (SPI)
5.4.9 Analog-to-Digital (A/D) Converter
5.4.10 System
5.5 Reset and Interrupt Priority
M68HC11E Family — Rev. 3.2
MOTOROLA
The SPI system is disabled by reset. The port pins associated with this
function default to being general-purpose I/O lines.
The analog-to-digital (A/D) converter configuration is indeterminate after
reset. The ADPU bit is cleared by reset, which disables the A/D system.
The conversion complete flag is indeterminate.
The EEPROM programming controls are disabled, so the memory
system is configured for normal read operation. PSEL[3:0] are initialized
with the value %0110, causing the external IRQ pin to have the highest
I-bit interrupt priority. The IRQ pin is configured for level-sensitive
operation (for wired-OR systems). The RBOOT, SMOD, and MDA bits in
the HPRIO register reflect the status of the MODB and MODA inputs at
the rising edge of reset. MODA and MODB inputs select one of the four
operating modes. After reset, writing SMOD and MDA in special modes
causes the MCU to change operating modes. Refer to the description of
HPRIO register in
for a detailed description of SMOD and MDA. The DLY control bit is set
to specify that an oscillator startup delay is imposed upon recovery from
stop mode. The clock monitor system is disabled because CME is
cleared.
Resets and interrupts have a hardware priority that determines which
reset or interrupt is serviced first when simultaneous requests occur. Any
maskable interrupt can be given priority over other maskable interrupts.
Resets and Interrupts
Section 4. Operating Modes and On-Chip Memory
Reset and Interrupt Priority
Resets and Interrupts
Technical Data
117

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