MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 123

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5.6.2 Non-Maskable Interrupt Request (XIRQ)
5.6.3 Illegal Opcode Trap
M68HC11E Family — Rev. 3.2
MOTOROLA
Non-maskable interrupts are useful because they can always interrupt
CPU operations. The most common use for such an interrupt is for
serious system problems, such as program runaway or power failure.
The XIRQ input is an updated version of the NMI (non-maskable
interrupt) input of earlier MCUs.
Upon reset, both the X bit and I bit of the CCR are set to inhibit all
maskable interrupts and XIRQ. After minimum system initialization,
software can clear the X bit by a TAP instruction, enabling XIRQ
interrupts. Thereafter, software cannot set the X bit. Thus, an XIRQ
interrupt is a non-maskable interrupt. Because the operation of the
I-bit-related interrupt structure has no effect on the X bit, the internal
XIRQ pin remains unmasked. In the interrupt priority logic, the XIRQ
interrupt has a higher priority than any source that is maskable by the
I bit. All I-bit-related interrupts operate normally with their own priority
relationship.
When an I-bit-related interrupt occurs, the I bit is automatically set by
hardware after stacking the CCR byte. The X bit is not affected. When
an X-bit-related interrupt occurs, both the X and I bits are automatically
set by hardware after stacking the CCR. A return-from-interrupt
instruction restores the X and I bits to their pre-interrupt request state.
Because not all possible opcodes or opcode sequences are defined, the
MCU includes an illegal opcode detection circuit, which generates an
interrupt request. When an illegal opcode is detected and the interrupt is
recognized, the current value of the program counter is stacked. After
interrupt service is complete, reinitialize the stack pointer so repeated
execution of illegal opcodes does not cause stack underflow. Left
uninitialized, the illegal opcode vector can point to a memory location
that contains an illegal opcode. This condition causes an infinite loop
that causes stack underflow. The stack grows until the system crashes.
The illegal opcode trap mechanism works for all unimplemented
opcodes on all four opcode map pages. The address stacked as the
Resets and Interrupts
Resets and Interrupts
Technical Data
Interrupts
123

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