MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 151

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7 SCI Error Detection
M68HC11E Family — Rev. 3.2
MOTOROLA
there is a loss of efficiency because of the extra bit time for each
character (address bit) required for all characters.
Three error conditions – SCDR overrun, received bit noise, and
framing – can occur during generation of SCI system interrupts. Three
bits (OR, NF, and FE) in the serial communications status register
(SCSR) indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be
transferred from the receive shift register to the SCDR and the SCDR is
already full (RDRF bit is set). When an overrun error occurs, the data
that caused the overrun is lost and the data that was already in SCDR is
not disturbed. The OR is cleared when the SCSR is read (with OR set),
followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits,
including the start and stop bits. The NF bit is not set until the RDRF flag
is set. The NF bit is cleared when the SCSR is read (with FE equal to 1)
followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing
error (FE) bit is set. FE is set at the same time as the RDRF. If the byte
received causes both framing and overrun errors, the processor only
recognizes the overrun error. The framing error flag inhibits further
transfer of data into the SCDR until it is cleared. The FE bit is cleared
when the SCSR is read (with FE equal to 1) followed by a read of the
SCDR.
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI Error Detection
Technical Data
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