MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 166

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
8.2 Introduction
8.3 Functional Description
Technical Data
166
The serial peripheral interface (SPI), an independent serial
communications subsystem, allows the MCU to communicate
synchronously with peripheral devices, such as:
The SPI is also capable of inter-processor communication in a multiple
master system. The SPI system can be configured as either a master or
a slave device. When configured as a master, data transfer rates can be
as high as one-half the E-clock rate (1.5 Mbits per second for a 3-MHz
bus frequency). When configured as a slave, data transfers can be as
fast as the E-clock rate (3 Mbits per second for a 3-MHz bus frequency).
The central element in the SPI system is the block containing the shift
register and the read data buffer. The system is single buffered in the
transmit direction and double buffered in the receive direction. This
means that new data for transmission cannot be written to the shifter
until the previous transfer is complete; however, received data is
transferred into a parallel read data buffer so the shifter is free to accept
a second serial character. As long as the first character is read out of the
read data buffer before the next serial character is ready to be
transferred, no overrun condition occurs. A single MCU register address
is used for reading data from the read data buffer and for writing data to
the shifter.
The SPI status block represents the SPI status functions (transfer
complete, write collision, and mode fault) performed by the serial
peripheral status register (SPSR). The SPI control block represents
those functions that control the SPI system through the serial peripheral
control register (SPCR).
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Frequency synthesizers
Liquid crystal display (LCD) drivers
Analog-to-digital (A/D) converter subsystems
Other microprocessors
Serial Peripheral Interface (SPI)
M68HC11E Family — Rev. 3.2
MOTOROLA