MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 184

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing System
9.4.2 Timer Input Capture Registers
Technical Data
184
Register name: Timer Input Capture 1 Register (High)
Register name: Timer Input Capture 1 Register (Low)
When an edge has been detected and synchronized, the 16-bit
free-running counter value is transferred into the input capture register
pair as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2
clock so that the count value is stable whenever a capture occurs. The
timer input capture registers are not affected by reset. Input capture
values can be read from a pair of 8-bit read-only registers. A read of the
high-order byte of an input capture register pair inhibits a new capture
transfer for one bus cycle. If a double-byte read instruction, such as load
double accumulator D (LDD), is used to read the captured value,
coherency is assured. When a new input capture occurs immediately
after a high-order byte read, transfer is delayed for an additional cycle
but the value is not lost.
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 9-4. Timer Input Capture 1 Register Pair (TIC1)
Bit 15
Bit 7
Bit 7
Bit 7
Bit 14
Bit 6
Timing System
6
6
Bit 13
Bit 5
5
5
Indeterminate after reset
Indeterminate after reset
Bit 12
Bit 4
4
4
Address: $1011
Address: $1010
Bit 11
Bit 3
3
3
M68HC11E Family — Rev. 3.2
Bit 10
Bit 2
2
2
Bit 9
Bit 1
1
1
MOTOROLA
Bit 0
Bit 8
Bit 0
Bit 0