MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 190

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Timing System
9.5.2 Timer Compare Force Register
Technical Data
190
Address:
The CFORC register allows forced early compares. FOC[1:5]
correspond to the five output compares. These bits are set for each
output compare that is to be forced. The action taken as a result of a
forced compare is the same as if there were a match between the OCx
register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their
programmed pin actions to occur at the next timer count transition after
the write to CFORC.
The CFORC bits should not be used on an output compare function that
is programmed to toggle its output on a successful compare because a
normal compare that occurs immediately before or after the force can
result in an undesirable operation.
FOC[1:5] — Force Output Comparison Bit
Bits [2:0] — Unimplemented
Reset:
Read:
Write:
When the FOC bit associated with an output compare circuit is set,
the output compare circuit immediately performs the action it is
programmed to do when an output match occurs.
Always read 0
0 = Not affected
1 = Output x action occurs
Figure 9-12. Timer Compare Force Register (CFORC)
$100B
FOC1
Bit 7
0
= Unimplemented
FOC2
Timing System
6
0
FOC3
5
0
FOC4
4
0
FOC5
3
0
M68HC11E Family — Rev. 3.2
2
0
1
0
MOTOROLA
Bit 0
0

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