MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 199

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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9.6 Real-Time Interrupt (RTI)
M68HC11E Family — Rev. 3.2
MOTOROLA
The real-time interrupt (RTI) feature, used to generate hardware
interrupts at a fixed periodic rate, is controlled and configured by two bits
(RTR1 and RTR0) in the pulse accumulator control (PACTL) register.
The RTII bit in the TMSK2 register enables the interrupt capability. The
four different rates available are a product of the MCU oscillator
frequency and the value of bits RTR[1:0]. Refer to
shows the periodic real-time interrupt rates.
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. This clock causes the time
between successive RTI timeouts to be a constant that is independent
of the software latencies associated with flag clearing and service. For
this reason, an RTI period starts from the previous timeout, not from
when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set,
an interrupt request is generated. After reset, one entire RTI period
elapses before the RTIF is set for the first time. Refer to the
Interrupt Mask 2
9.6.3 Pulse Accumulator Control
RTR[1:0]
0 0
0 1
1 0
1 1
E = 3 MHz
10.923 ms
21.845 ms
2.731 ms
5.461 ms
Timing System
Register,
Table 9-5. RTI Rates
9.6.2 Timer Interrupt Flag Register
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
Register.
E = 1 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
Real-Time Interrupt (RTI)
Table
9-5, which
Timing System
Technical Data
9.5.9 Timer
E = X MHz
(E/2
(E/2
(E/2
(E/2
13
14
15
16
2, and
)
)
)
)
199

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