MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 295

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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AN1060 — Rev. 1.0
MOTOROLA
jumper must be installed across J3 to configure the master MCU for
bootstrap mode.
One MC68HC711E9 is first programmed by other means with a desired
12-Kbyte program in its EPROM and a small duplicator program in its
EEPROM. Alternately, the ROM program in an MC68HC11E9 can be
copied into the EPROM of a target MC68HC711E9 by programming only
the duplicator program into the EEPROM of the master MC68HC11E9.
The master MCU is installed in the EVBU at socket U3. A blank
MC68HC711E9 to be programmed is placed in the socket in the wire-
wrap area of the EVBU (U6).
With the V
power is applied to the EVBU, the master MCU (U3) comes out of reset
in bootstrap mode. Target MCU (U6) is held in reset by the PB7 output
of master MCU (U3). The PB7 output of U3 is forced to 0 when U3 is
reset. The master MCU will later release the reset signal to the target
MCU under software control. The RxD and TxD pins of the target MCU
(U6) are high-impedance inputs while U6 is in reset so they will not affect
the TxD and RxD signals of the master MCU (U3) while U3 is coming out
of reset. Since the target MCU is being held in reset with MODA and
MODB at 0, it is configured for the PROG EPROM emulation mode, and
PB7 is the output enable signal for the EPROM data I/O (input/output)
pins. Pullup resistor R7 causes the port D pins, including RxD and TxD,
to remain in the high-impedance state so they do not interfere with the
RxD and TxD pins of the master MCU as it comes out of reset.
As U3 leaves reset, its mode pins select bootstrap mode so the
bootloader firmware begins executing. A break is sent out the TxD pin of
U3. Pullup resistor R10 and resistor R9 cause the break character to be
seen at the RxD pin of U3. The bootloader performs a jump to the start
of EEPROM in the master MCU (U3) and starts executing the duplicator
program. This sequence demonstrates how to use bootstrap mode to
pass control to the start of EEPROM after reset.
The complete listing for the duplicator program in the EEPROM of the
master MCU is provided in
Program.
PP
power switch off, power is applied to the EVBU system. As
Listing 1. MCU-to-MCU Duplicator
Application Note
295

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