MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 315

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bootloading
a Program
to Perform
a ROM Checksum
Inherent Delays
Caused
by Double
Buffering
of SCI Data
AN1060 — Rev. 1.0
MOTOROLA
The port pins that are used for EPROM data I/O lines may be inputs or
outputs, depending on the pin that is emulating the EPROM output
enable pin (OE). To make these data pins appear as high-impedance
inputs as they would on a non-EPROM part in reset, connect the
PB7/(OE) pin to a pullup resistor.
The bootloader ROM must be turned off before performing the
checksum program. To remove the boot ROM from the memory map,
clear the RBOOT bit in the HPRIO register. This is normally a write-
protected bit that is 0, but in bootstrap mode it is reset to 1 and can be
written. If the boot ROM is not disabled, the checksum routine will read
the contents of the boot ROM rather than the user’s mask ROM or
EPROM at the same addresses.
This problem is troublesome in cases where one MCU is bootloading to
another MCU.
Because of transmitter double buffering, there may be one character in
the serial shifter as a new character is written into the transmit data
register. In cases such as downloading in which this 2-character pipeline
is kept full, a 2-character time delay occurs between when a character is
written to the transmit data register and when that character finishes
transmitting. A little more than one more character time delay occurs
between the target MCU receiving the character and echoing it back. If
the master MCU waits for the echo of each downloaded character before
sending the next one, the download process takes about twice as long
as it would if transmission is treated as a separate process or if verify
data is ignored.
Application Note
315