MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 36

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
2.6 E-Clock Output (E)
2.7 Interrupt Request (IRQ)
2.8 Non-Maskable Interrupt (XIRQ/V
Technical Data
36
NOTE:
E is the output connection for the internally generated E clock. The signal
from E is used as a timing reference. The frequency of the E-clock output
is one fourth that of the input frequency at the XTAL and EXTAL pins.
When E-clock output is low, an internal process is taking place. When it
is high, data is being accessed.
All clocks, including the E clock, are halted when the MCU is in stop
mode. To reduce RFI emissions, the E-clock output of most E-series
devices can be disabled while operating in single-chip modes.
The E-clock signal is always enabled on the MC68HC811E2.
The IRQ input provides a means of applying asynchronous interrupt
requests to the MCU. Either negative edge-sensitive triggering or
level-sensitive triggering is program selectable (OPTION register). IRQ
is always configured to level-sensitive triggering at reset. When using
IRQ in a level-sensitive wired-OR configuration, connect an external
pullup resistor, typically 4.7 k , to V
The XIRQ input provides a means of requesting a non-maskable
interrupt after reset initialization. During reset, the X bit in the condition
code register (CCR) is set and any interrupt is masked until MCU
software enables it. Because the XIRQ input is level-sensitive, it can be
connected to a multiple-source wired-OR network with an external pullup
resistor to V
Whenever XIRQ or IRQ is used with multiple interrupt sources each
source must drive the interrupt input with an open-drain type of driver to
avoid contention between outputs.
IRQ must be configured for level-sensitive operation if there is more than
one source of IRQ interrupt.
DD
. XIRQ is often used as a power loss detect interrupt.
Pin Descriptions
PPE
)
DD
.
M68HC11E Family — Rev. 3.2
MOTOROLA