MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 37

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9 MODA and MODB (MODA/LIR and MODB/V
M68HC11E Family — Rev. 3.2
MOTOROLA
There should be a single pullup resistor near the MCU interrupt input pin
(typically 4.7 k ). There must also be an interlock mechanism at each
interrupt source so that the source holds the interrupt line low until the
MCU recognizes and acknowledges the interrupt request. If one or more
interrupt sources are still pending after the MCU services a request, the
interrupt line will still be held low and the MCU will be interrupted again
as soon as the interrupt mask bit in the MCU is cleared (normally upon
return from an interrupt). Refer to
V
for EPROM/OTPROM programming. On devices without
EPROM/OTPROM, this pin is only an XIRQ input.
During reset, MODA and MODB select one of the four operating modes:
Refer to
After the operating mode has been selected, the load instruction register
(LIR) pin provides an open-drain output to indicate that execution of an
instruction has begun. A series of E-clock cycles occurs during
execution of each instruction. The LIR signal goes low during the first
E-clock cycle of each instruction (opcode fetch). This output is provided
for assistance in program debugging.
The V
power. When the voltage on this pin is more than one MOS threshold
(about 0.7 volts) above the V
reset logic are powered from this signal rather than the V
allows RAM contents to be retained without V
MCU. Reset must be driven low before V
low until V
PPE
•
•
•
•
is the input for the 12-volt nominal programming voltage required
STBY
Single-chip mode
Expanded mode
Test mode
Bootstrap mode
Section 4. Operating Modes and On-Chip
DD
pin is used to input random-access memory (RAM) standby
has been restored to a valid level.
Pin Descriptions
DD
MODA and MODB (MODA/LIR and MODB/VSTBY)
voltage, the internal RAM and part of the
Section 5. Resets and
STBY
DD
)
is removed and must remain
DD
power applied to the
Memory.
DD
Pin Descriptions
Interrupts.
Technical Data
input. This
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