MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 54

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Central Processor Unit (CPU)
3.6 Addressing Modes
3.6.1 Immediate
Technical Data
54
A 4-page opcode map has been implemented to expand the number of
instructions. An additional byte, called a prebyte, directs the processor
from page 0 of the opcode map to one of the other three pages. As its
name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero,
one, two, or three operands. The operands contain information the CPU
needs for executing the instruction. Complete instructions can be from
one to five bytes long.
Six addressing modes can be used to access memory:
These modes are detailed in the following paragraphs. All modes except
inherent mode use an effective address. The effective address is the
memory address from which the argument is fetched or stored or the
address from which execution is to proceed. The effective address can
be specified within an instruction, or it can be calculated.
In the immediate addressing mode, an argument is contained in the
byte(s) immediately following the opcode. The number of bytes following
the opcode matches the size of the register or memory location being
operated on. There are 2-, 3-, and 4- (if prebyte is required) byte
immediate instructions. The effective address is the address of the byte
following the instruction.
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Immediate
Direct
Extended
Indexed
Inherent
Relative
Central Processor Unit (CPU)
M68HC11E Family — Rev. 3.2
MOTOROLA