MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 57

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
BCLR (opr)
ADDD (opr)
ADCA (opr)
ADCB (opr)
ADDA (opr)
ADDB (opr)
ANDA (opr)
ANDB (opr)
Mnemonic
ASL (opr)
BCC (rel)
ASLD
ASRA
ASRB
ASLA
ASLB
ABA
ABX
ABY
ASR
(msk)
Add Memory to
Add Memory to
Add 16-Bit to D
Arithmetic Shift
Arithmetic Shift
Arithmetic Shift
Arithmetic Shift
Arithmetic Shift
Arithmetic Shift
Arithmetic Shift
Branch if Carry
Add with Carry
Add with Carry
Accumulators
AND A with
AND B with
Clear Bit(s)
Operation
Add B to X
Add B to Y
Memory
Memory
Right A
Right B
Left A
Left B
Left D
Clear
Right
Add
to A
to B
Left
A
B
D + (M : M + 1)
C
IX + (00 : B)
IY + (00 : B)
C
C
C
A + M + C
B + M + C
M • (mm)
b7
Description
b7
b7
b7
A + M
B + M
A + B
A • M
B • M
b7
b7
b7
A
? C = 0
b0
Table 3-2. Instruction Set (Sheet 1 of 7)
b7
b0
b0
b0
B
A
A
B
B
b0
b0
b0
A
b0
M
A
B
C
C
C
IX
IY
0
0
0
0
D
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
A
B
A
B
Central Processor Unit (CPU)
Addressing
Mode
INH
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
REL
DIR
IND,X
IND,Y
18
18
18
18
18
18
18
18
18
18
18
Opcode
1B
3A
3A
89
99
A9
A9
C9
D9
E9
E9
8B
9B
AB
AB
CB
DB
EB
EB
C3
D3
E3
E3
84
94
A4
A4
C4
D4
E4
E4
78
68
68
48
58
05
77
67
67
47
57
24
15
1D
1D
B9
F9
BB
FB
F3
B4
F4
Instruction
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
hh ll
ff
ff
rr
dd mm
ff mm
ff mm
Operand
—
—
—
—
—
—
—
—
Cycles
2
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
2
2
3
6
6
7
2
2
3
6
7
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
Central Processor Unit (CPU)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H
Condition Codes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
—
—
—
N
Technical Data
Instruction Set
—
—
—
Z
—
—
—
V
0
0
0
—
—
—
—
—
—
C
57