MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 63

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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M68HC11E Family — Rev. 3.2
MOTOROLA
Cycle
*
**
Operands
dd
ff
hh
ii
jj
kk
ll
mm
rr
Operators
( )
+
:
Mnemonic
TST (opr)
XGDX
XGDY
TEST
TSTA
TSTB
TPA
TSX
TSY
TXS
TYS
WAI
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
= High-order byte of 16-bit extended address
= One byte of immediate data
= High-order byte of 16-bit immediate data
= Low-order byte of 16-bit immediate data
= Low-order byte of 16-bit extended address
= 8-bit mask (set bits to be affected)
= Signed relative offset $80 (–128) to $7F (+127)
Contents of register shown inside parentheses
Is transferred to
Is pulled from stack
Is pushed onto stack
Boolean AND
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction symbol or negation symbol (two’s complement)
(offset relative to address following machine code offset byte))
Test for Zero or
Test A for Zero
Test B for Zero
Transfer Stack
Transfer Stack
TEST (Only in
Register to A
Transfer X to
Stack Pointer
Transfer Y to
Stack Pointer
Test Modes)
Transfer CC
Exchange D
Exchange D
Pointer to X
Pointer to Y
Operation
or Minus
or Minus
Interrupt
Wait for
with X
with Y
Minus
Address Bus Counts
Stack Regs & WAIT
IX
IY
Description
SP + 1
SP + 1
IX – 1
IY – 1
CCR
M – 0
A – 0
B – 0
D, D
D, D
Table 3-2. Instruction Set (Sheet 7 of 7)
SP
SP
A
IX
IY
IX
IY
A
B
Central Processor Unit (CPU)
Addressing
Mode
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
INH
INH
INH
18
18
18
18
Opcode
3E
00
07
7D
6D
6D
4D
5D
30
30
35
35
8F
8F
Instruction
Condition Codes
0
1
hh ll
ff
ff
Operand
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
Cycles
**
2
6
6
7
2
2
3
4
3
4
3
4
*
S
Central Processor Unit (CPU)
X
H
Condition Codes
I
N
Technical Data
Instruction Set
Z
V
0
0
0
C
0
0
0
63

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