DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 1042
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1042 of 1208
- Download datasheet (8Mb)
Section 24 Power-Down Modes
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Clearing with the RES Pin:
When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation
starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock
oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Clearing with the STBY Pin:
When the STBY pin is driven low, a transition is made to hardware standby mode.
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to
STS0 in SBYCR should be set as described below.
Using a Crystal Resonator:
Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 24.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0.
Using an External Clock:
A PLL circuit stabilization time is necessary. Refer to table 24.2 to set the wait time.
Rev.7.00 Mar. 18, 2009 page 974 of 1136
REJ09B0109-0700
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