DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 403
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 403 of 1208
- Download datasheet (8Mb)
Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated
during data transfer, block transfer operation is not affected until data transfer for one block has
ended.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Address bus
TEND
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
HWR
Bus release
LWR
RD
φ
DMA
read
DMA
write
Block transfer
DMA
read
DMA
write
DMA
dead
Bus release
Rev.7.00 Mar. 18, 2009 page 335 of 1136
DMA
read
DMA
Section 7 DMA Controller (DMAC)
write
Last block transfer
DMA
read
DMA
write
REJ09B0109-0700
DMA
dead
Bus
release
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