DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 454
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 454 of 1208
- Download datasheet (8Mb)
Section 8 EXDMA Controller (EXDMAC)
accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The
address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented
when SAT1 = 1 and SAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
Do not write to EDSAR for a channel on which a transfer operation is in progress.
EXDMA Destination Address Register (EDDAR): When the EDDAR address is accessed as the
transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be
accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The
address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented
when DAT1 = 1 and DAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
Do not write to EDDAR for a channel on which a transfer operation is in progress.
Rev.7.00 Mar. 18, 2009 page 386 of 1136
REJ09B0109-0700
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