DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 612
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 612 of 1208
- Download datasheet (8Mb)
Section 10 I/O Ports
• PH1/CS5/RAS5/SDRAMφ *
Notes: 1. When SDRAM interface is not used, input a low-level signal on the DCTL pin.
• PH0/CS4/RAS4/WE *
Note:
Rev.7.00 Mar. 18, 2009 page 544 of 1136
REJ09B0109-0700
DCTL *
Operating
mode
EXPE
Area 5
DCTL
CS5E
PH1DDR
Pin function
Operating
mode
EXPE
Area 4
CS4E
PH0DDR
Pin function
The pin function is switched as shown below according to the operating mode, DCTL pin, bit
EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.
1
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
* Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
input
input
PH1
PH0
H8S/2373.
H8S/2373.
0
0
0
⎯
0
Normal space
output
PH1
output
1
PH0
1
input
PH1
0
input
Normal space
PH0
1
0
output
1, 2, 4
CS5
1, 2, 4
1
⎯
⎯
output
CS4
input
1
PH1
0
2
DRAM space
0
1
output
DRAM
output
space
RAS4
PH1
⎯
1
output
RAS5
chronous
DRAM *
⎯
output
space
1
WE *
Syn-
⎯
input
PH1
0
input
PH0
⎯
⎯
0
0
0
0
output
PH1
1
⎯
⎯
0
output
PH0
input
1
PH1
0
0
Normal space
output
input
PH1
PH0
1
0
⎯
0
input
PH1
output
0
PH0
7
1
1
output
CS5
1
7
1
input
Normal space
PH0
0
input
PH1
0
DRAM space
1
output
0
CS4
output
1
PH1
1
1
DRAM
output
space
RAS4
output
RAS5
⎯
⎯
1
SDRAM *
chronous
φ output
DRAM *
output
space
WE *
Syn-
⎯
⎯
⎯
⎯
⎯
⎯
1
1
2
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