DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 121
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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3.2.2
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit
7
6
5
4
3
Bit Name
CS2E
IOSE
INTM1
INTM0
XRST
System Control Register (SYSCR)
Initial Value
0
0
0
0
1
R/W
R/W
R/W
R
R/W
R
Description
Chip Select 2 Enable
Specifies the location of the control pin (CS2) of the
host interface together with the FGA20E bit in HICR.
See section 18, Host Interface X-Bus Interface (XBS),
for details.
IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
1: IOS pin
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see section
5.6, Interrupt Control Modes and Interrupt Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
1: A reset is caused by an external reset.
Outputs low when an external area is accessed.
Outputs low when a specified address of addresses
H'(FF)F000 to H'(FF)F7FF is accessed.
overflows.
Rev. 3.00 Mar 21, 2006 page 65 of 788
Section 3 MCU Operating Modes
REJ09B0300-0300
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