DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 180

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Section 6 Bus Controller (BSC)
6.3.1
BCR is used to specify the access mode for the external address space or the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 21, 2006 page 124 of 788
REJ09B0300-0300
Bit Name
—
ICIS0
BRSTRM
BRSTS1
BRSTS0
IOS1
IOS0
Bus Control Register (BCR)
Initial Value
1
1
0
1
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit should not be written by 0.
Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle
cycle between bus cycles when the external write
cycle follows the external read cycle.
0: Idle cycle not inserted when the external write cycle
1: 1-state idle cycle inserted when the external write
Burst ROM Enable
Selects the bus interface for the external address
space.
0: Basic bus interface
1: Burst ROM interface
Burst Cycle Select 1
Selects the number of states in the burst cycle of the
burst ROM interface.
0: 1 state
1: 2 states
Burst Cycle Select 0
Selects the number of words that can be accessed by
burst access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
Reserved
This bit should not be written by 0.
IOS Select 1, 0
Select the address range where the IOS signal is
output. For details, refer to table 6.3.
follows the external read cycle
cycle follows the external read cycle