DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 185
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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6.5
The basic bus interface enables direct connection to ROM and SRAM. For details on selection of
the bus specifications when using the basic bus interface, see table 6.2
6.5.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus
(D7 to D0) is used when the external address space is accessed, according to the bus specifications
for the area being accessed (8-bit access space or 16-bit access space) and the data size.
8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Basic Bus Interface
Data Size and Data Alignment
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
D15
Upper data bus
Rev. 3.00 Mar 21, 2006 page 129 of 788
D8 D7
Section 6 Bus Controller (BSC)
Lower data bus
D0
REJ09B0300-0300
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