DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 205

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

7.2.2
MRB selects the DTC operating mode.
7.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Bit
7
6
5
to
0
Bit Name
CHNE
DISEL
—
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
DTC Destination Address Register (DAR)
Initial Value
Undefined
Undefined
Undefined
R/W
—
—
—
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 7.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends (the DTC
clears the interrupt source flag for the activation
source). When this bit is cleared to 0, a CPU interrupt
request is generated only when the specified number of
data transfer ends (the DTC does not clear the interrupt
source flag for the activation source).
Reserved
These bits have no effect on DTC operation. Only 0
should be written to these bits.
Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Mar 21, 2006 page 149 of 788
REJ09B0300-0300