DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 24
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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2.8
2.9
Section 3 MCU Operating Modes
3.1
3.2
3.3
3.4
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
Rev. 3.00 Mar 21, 2006 page xxii of liv
2.7.8
2.7.9
Processing States............................................................................................................... 57
Usage Notes ...................................................................................................................... 59
2.9.1
2.9.2
2.9.3
2.9.4
MCU Operating Mode Selection ...................................................................................... 63
Register Descriptions ........................................................................................................ 63
3.2.1
3.2.2
3.2.3
Operating Mode Descriptions ........................................................................................... 69
3.3.1
3.3.2
3.3.3
3.3.4
Address Map in Each Operating Mode ............................................................................. 71
Exception Handling Types and Priority ............................................................................ 81
Exception Sources and Exception Vector Table ............................................................... 82
Reset.................................................................................................................................. 83
4.3.1
4.3.2
4.3.3
Interrupt Exception Handling............................................................................................ 85
Trap Instruction Exception Handling................................................................................ 85
Stack Status after Exception Handling.............................................................................. 86
Usage Note........................................................................................................................ 87
Features ............................................................................................................................. 89
Input/Output Pins .............................................................................................................. 91
Register Descriptions ........................................................................................................ 91
5.3.1
5.3.2
5.3.3
Memory Indirect—@@aa:8 ................................................................................ 54
Effective Address Calculation ............................................................................. 55
Note on TAS Instruction Usage ........................................................................... 59
Note on STM/LDM Instruction Usage ................................................................ 59
Note on Bit Manipulation Instructions................................................................. 59
EEPMOV Instruction........................................................................................... 61
Mode Control Register (MDCR) ......................................................................... 64
System Control Register (SYSCR) ...................................................................... 65
Serial Timer Control Register (STCR) ................................................................ 66
Mode 1 ................................................................................................................. 69
Mode 2 ................................................................................................................. 69
Mode 3 ................................................................................................................. 69
Pin Functions in Each Operating Mode ............................................................... 70
Reset Exception Handling.................................................................................... 83
Interrupts after Reset............................................................................................ 84
On-Chip Peripheral Modules after Reset Is Cancelled ........................................ 84
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 92
Address Break Control Register (ABRKCR)....................................................... 93
Break Address Registers A to C (BARA to BARC) ............................................ 94
.......................................................................................... 89
......................................................................................... 81
.................................................................................. 63
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